Arteris unveils new Magillem Registers to boost SoC design
Arteris has announced the release of the latest generation of its Magillem Registers technology, designed to streamline the integration process for system-on-chip (SoC) design.
This update promises to significantly reduce development time by 35% compared to traditional in-house solutions, providing design teams with enhanced capabilities for integrating hardware and software components in SoCs. The Magillem Registers consolidate the previously separate Magillem 5 and Semifore CSRCompiler into a scalable solution.
According to Arteris, this new release of Magillem Registers boosts performance. It improves scalability by fivefold, addressing the needs of various SoC designs, from simple IoT devices to complex artificial intelligence (AI) systems.
Magillem Registers are equipped to support the latest versions of industry standards, including IEEE 1685-2022 (IP-XACT) and SystemRDL 2.0. This support aims to simplify the design process and minimise costly errors by enhancing hardware/software integration capabilities.
K. Charles Janac, President and CEO of Arteris, said, "With over 70% of chips requiring respins, effectively addressing hardware and software integration has become quite a challenge for SoC teams, particularly given added complexity and growing chip sizes driven by the infusion of AI logic. Building AI SoCs and FPGAs is expensive and time-consuming, so automation efficiencies are critical to cost control and our latest release of Magillem Registers ensures that SoC engineering productivity is maximised and project risks are significantly reduced."
Magillem Registers are designed for a broad range of users, including chip architects, hardware designers, firmware engineers, verification teams, and documentation teams. The product aims to provide a unified infrastructure for specifying, documenting, implementing, and verifying SoC address maps, which could improve efficiency across the board due to its consistent approach.
The improvements in Magillem Registers include over 1,000 semantic and syntactic checks to ensure high-quality output, validate third-party IPs, in-house IPs, and overall system integration. Arteris claims this feature will efficiently reduce the risk of silicon failure.
Performance-wise, the latest Magillem Registers deliver up to three times the speed of its predecessor, allowing the compilation of millions of registers within minutes and auto-generating synthesisable RTL register banks for larger multi-die devices containing millions of control registers.
The product aims to increase productivity through a highly iterative and user-friendly design environment. Abuse enhancements reportedly allow more streamlined input, intuitive document navigation, and the elimination of repetitive manual tasks through advanced automation.
Arteris continues to offer solutions that address the increasing demands of modern design environments, aiming to support design teams in achieving efficient and scalable SoC integration processes.
