Intel achieves backside power delivery in silicon

In a first for the industry, Intel uses backside power delivery on a product-like test chip, resulting in 90% cell utilisation.

The test chip shows PowerVia's ability to deliver over 90% cell utilisation, solve growing interconnect bottlenecks and bring competitive advantages to customers, including foundry.

PowerVia, to be introduced on the Intel 20A process node in the first half of 2024, is Intel's innovative backside power delivery solution. 

Intel says surging use cases, including artificial intelligence and graphics, require smaller, denser and more powerful transistors to meet ever-growing computing demands. Power and signal lines within a transistor's architecture have competed for the same resources for decades. 

By separating the two, chips can increase performance and energy efficiency and deliver better results for customers. 

Therefore Backside power delivery is vital to transistor scaling, enabling chip designers to increase transistor density without sacrificing resources to deliver more power and performance than ever.  

PowerVia gives chip designers, including Intel Foundry Services (IFS) customers, a faster path to valuable energy and performance gains in their products. 

Ben Sell, Vice President of Technology Development, Intel, says: "PowerVia is a major milestone in our aggressive 'five nodes in four years' strategy and on our path to achieving a trillion transistors in a package in 2030." 

"Using a trial process node and subsequent test chip enabled us to de-risk backside power for our leading process nodes, placing Intel a node ahead of competitors in bringing backside power delivery to market."

Intel decoupled the development of PowerVia from transistor development to ensure its readiness for silicon implementation based on Intel 20A and Intel 18A process nodes. It was then tested on its internal test node to debug and ensure functionality before integrating with RibbonFET in Intel 20A.

After fabrication and testing on a silicon test chip, PowerVia was confirmed to bring a remarkably efficient use of chip resources with greater than 90% cell utilisation and significant transistor scaling, enabling chip designers to achieve performance and efficiency gains in their products.  

Intel will present these findings in two papers at the VLSI Symposium on June 11-16 in Kyoto, Japan. 

Intel has a notable history of introducing significant advancements in the technology industry, such as strained silicon, Hi-K metal gate and FinFET, propelling Moore's Law forward. 

With PowerVia and RibbonFET gate-all-around technology coming in 2024, Intel continues accelerating the chip design and process innovations industry. Intel 20A and Intel 18A will introduce both PowerVia backside power technology and RibbonFET gate-all-around technology. 

As an entirely new way of delivering power to the transistors, backside power implementation raised new challenges for thermals and debugging designs.  

By decoupling the development of PowerVia from RibbonFET, Intel could work through those challenges quickly to ensure readiness for implementation in silicon based on Intel's 20A and 18A process nodes. 

Intel engineers developed mitigation techniques to prevent the thermals from becoming an issue. The debug community also developed new techniques to ensure the new design structure could be appropriately debugged. 

As a result, the test implementation delivered solid yield and reliability metrics while demonstrating the intrinsic value proposition of the technology well before it joins the new RibbonFET architecture. 

The test also leveraged design rules enabled by EUV (extreme ultraviolet) lithography, which produced results including standard cell utilisation of more than 90% over large areas of the die, enabling greater cell density, which can be expected to lower costs. 

Additionally, it showed more than 30% platform voltage droop improvement and a 6% frequency benefit. Intel also achieved thermal characteristics in the PowerVia test chip in line with higher power densities expected from logic scaling. 

In a third paper to be presented during VLSI, Intel technologist Mauro Kobrinsky will explain Intel's research into more advanced methods to deploy PowerVia, such as enabling signalling and power delivery on either the front or the back side of the wafer. 

Bringing PowerVia to customers and continuing to innovate into the future is in keeping with Intel's long history of bringing new semiconductor innovations to the market.